Static RAM (Static Random Access Memory) is ubiquitous in current integrated circuits as the work horse for on-chip cache memory. However, SRAM cells are large and do not scale well (cell size becomes increasingly larger in terms of F2 and the static leakage increases). Especially at higher caching levels (L3 and L4), the area penalty is substantial.
SRAM cells typically comprise 6 transistors. This has its consequences for the size of an SRAM cell and for the power consumption of the SRAM cell. In the case of 2D planar design the size of an SRAM cell with 6 transistors typically is larger than 150 F2, wherein F is the smallest linewidth. This size increases with scaling.
Therefore, there is a strong motivation to investigate other memory cell concepts. Some conventional memory cells, however, have an access speed which is much smaller than SRAM. Examples thereof are NOR, 1T1R, 1T1C.
Alternatives are searched to decrease the area and power consumption of the SRAM. A possible alternative is spin-transfer-torque magnetoresistive random access memory (STT-MRAM). There are, however, still different issues to be solved for STT-MRAM (e.g. processing issues). STT-MRAM could be a possible replacement candidate for SRAM, but only on the long term.
There is therefore still room for alternatives for SRAM which have a smaller area per cell than SRAM.